1. Field of the Invention
The present invention relates to host bus adapters, and more particularly, to minimizing corruption of memory used by host bus adapters.
2. Background of the Invention
A Host bus adapter (may also be referred to as “controller”, “adapter” or “HBA”) is an adapter placed between a host system computer bus and a network (fibre channel system, Ethernet, Gigabit Ethernet, or any other system). HBAs manage transfer of information between the host system and the network. To minimize the impact on host processor performance, HBAs perform various interface functions automatically or with minimal host processor involvement.
HBAs are connected to a host system via standard buses. One such bus is the Peripheral Component Interconnect (“PCI”), a standard bus developed by Intel Corporation®, incorporated herein by reference in its entirety. PCI is a 64-bit bus, though it is usually implemented as a 32-bit bus. It can run at clock speeds of 33 or 66 MHz. At 32 bits and 33 MHz, it yields a throughput rate of 133 MBps.
PCI-X is another standard bus that is backward compatible with existing PCI cards. The PCI-X standard is incorporated herein by reference in its entirety. PCI-X improves upon the speed of the PCI bus from 133 MBps to as much as 1 GBps. PCI-X was designed to increase performance of high bandwidth devices, such as Gigabit Ethernet and Fibre Channel.
Most HBAs are coupled to non-volatile random access memory (“NVRAM”) that allows HBAs to move information from a host and to/from the network. The problem with conventional HBAs using NVRAM is that the NVRAM may be erased accidentally when the HBA is powered on.
Typically, NVRAM control inputs are driven by general-purpose input/out (“GPIO”) pins from an HBA (or any other integrated circuit), which interfaces with a host system through a PCI backplane. At power up, and even sometimes during reset of the HBA, PCI backplanes drive noisy and non-deterministic waveforms on the RESET pin of the HBA. The GPIO pins can also drive unpredictable waveforms due to the PCI RESET behavior. One such waveform may issue an “ERASE” command to the NVRAM that erases NVRAM content.
As HBAs are being deployed in modern networks, with high bandwidth and performance requirements, such accidental erasure of information can be devastating to the overall performance of computing systems.
Therefore, what is needed is a method and system for preventing corruption of NVRAM information during power-up and/or reset.